View XCV150-5PQG240I_3932120.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 1999-2002 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as lis ted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. ds003-3 (v3.2) september 10, 2002 www.xilinx.com module 3 of 4 production product specification 1-800-255-7778 1 virtex electrical characteristics definition of terms electrical and switching characteristics are specified on a per-speed-grade basis and can be designated as advance, preliminary, or production. each designation is defined as follows: advance : these speed files are based on simulations only and are typically available soon after device design specifi- cations are frozen. although speed grades with this desig- nation are considered relatively stable and conservative, some under-reporting might still occur. preliminary : these speed files are based on complete es (engineering sample) silicon characterization. devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. the probability of under-reporting delays is greatly reduced as compared to advance data. production : these speed files are released once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subsequent changes. typ- ically, the slowest speed grades transition to production before faster speed grades. all specifications are representative of worst-case supply voltage and junction temperature conditions. the parame- ters included are common to popular designs and typical applications. contact the factory for design considerations requiring more detailed information. ta b l e 1 correlates the current status of each virtex device with a corresponding speed file designation. all specifications are subject to change without notice. 0 virtex? 2.5 v field programmable gate arrays ds003-3 (v3.2) september 10, 2002 00 production product specification r ta b l e 1 : virtex device speed grade designations device speed grade designations advance preliminary production xcv50 ?6, ?5, ?4 xcv100 ?6, ?5, ?4 xcv150 ?6, ?5, ?4 xcv200 ?6, ?5, ?4 xcv300 ?6, ?5, ?4 xcv400 ?6, ?5, ?4 xcv600 ?6, ?5, ?4 xcv800 ?6, ?5, ?4 xcv1000 ?6, ?5, ?4
virtex? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v3.2) september 10, 2002 2 1-800-255-7778 production product specification virtex dc characteristics absolute maximum ratings recommended operating conditions symbol description (1) units v ccint supply voltage relative to gnd (2) ? 0.5 to 3.0 v v cco supply voltage relative to gnd (2) ? 0.5 to 4.0 v v ref input reference voltage ? 0.5 to 3.6 v v in input voltage relative to gnd (3) using v ref ? 0.5 to 3.6 v internal threshold ? 0.5 to 5.5 v v ts voltage applied to 3-state output ? 0.5 to 5.5 v v cc longest supply voltage rise time from 1v-2.375v 50 ms t stg storage temperature (ambient) ? 65 to +150 c t j junction temperature (4) plastic packages +125 c notes: 1. stresses beyond those listed under absolute maximum ratings can cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating condi tions is not implied. exposure to absolute maximum ratings conditions for extended periods of time can affect device reliability. 2. power supplies can turn on in any order. 3. for protracted periods (e.g., longer than a day), v in should not exceed v cco by more than 3.6 v. 4. for soldering guidelines and thermal considerations, see the "device packaging" infomation on www.xilinx.com . symbol description min max units v ccint (1) input supply voltage relative to gnd, t j = 0 c to +85 ccommercial 2.5 ? 5% 2.5 + 5% v input supply voltage relative to gnd, t j = ? 40 c to +100 c industrial 2.5 ? 5% 2.5 + 5% v v cco (4) supply voltage relative to gnd, t j = 0 c to +85 ccommercial1.43.6v supply voltage relative to gnd, t j = ? 40 c to +100 c industrial 1.4 3.6 v t in input signal transition time 250 ns notes: 1. correct operation is guaranteed with a minimum v ccint of 2.375 v (nominal v ccint ? 5%). below the minimum value, all delay parameters increase by 3% for each 50-mv reduction in v ccint below the specified range. 2. at junction temperatures above those listed as operating conditions, delay parameters do increase. please refer to the trce r eport. 3. input and output measurement threshold is ~50% of v cc . 4. min and max values for v cco are i/o standard dependant.
virtex? 2.5 v field programmable gate arrays r ds003-3 (v3.2) september 10, 2002 www.xilinx.com module 3 of 4 production product specification 1-800-255-7778 3 dc characteristics over recommended operating conditions symbol description device min max units v drint data retention v ccint voltage (below which configuration data can be lost) all 2.0 v v drio data retention v cco voltage (below which configuration data can be lost) all 1.2 v i ccintq quiescent v ccint supply current (1,3) xcv50 50 ma xcv100 50 ma xcv150 50 ma xcv200 75 ma xcv300 75 ma xcv400 75 ma xcv600 100 ma xcv800 100 ma xcv1000 100 ma i ccoq quiescent v cco supply current (1) xcv50 2 ma xcv100 2 ma xcv150 2 ma xcv200 2 ma xcv300 2 ma xcv400 2 ma xcv600 2 ma xcv800 2 ma xcv1000 2 ma i ref v ref current per v ref pin all 20 a i l input or output leakage current all ? 10 +10 a c in input capacitance (sample tested) bga, pq, hq, packages all 8 pf i rpu pad pull-up (when selected) @ v in = 0 v, v cco = 3.3 v (sample tested) all note (2) 0.25 ma i rpd pad pull-down (when selected) @ v in = 3.6 v (sample tested) note (2) 0.15 ma notes: 1. with no output current loads, no active input pull-up resistors, all i/o pins 3-stated and floating. 2. internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. these pull-up and pull-down resistors do not guarantee valid logic levels when input pins are connected to other circuits. 3. multiply i ccintq limit by two for industrial grade.
virtex? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v3.2) september 10, 2002 4 1-800-255-7778 production product specification power-on power supply requirements xilinx fpgas require a certain amount of supply current during power-on to insure proper device operation. the actual current consumed depends on the power-on ramp rate of the power supply. this is the time required to reach the nominal power supply voltage of the device (1) from 0 v. the current is highest at the fastest suggested ramp rate (0 v to nominal voltage in 2 ms) and is lowest at the slowest allowed ramp rate (0 v to nominal voltage in 50 ms). for more details on power supply requirements, see application note xapp158 on www.xilinx.com . dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed output currents over the recommended operating conditions at the v ol and v oh test points. only selected standards are tested. these are chosen to ensure that all standards meet their specifications. the selected standards are tested at minimum v cco for each standard with the respective v ol and v oh voltage levels shown. other standards are sample tested. product description (2) current requirement (1,3) virtex family, commercial grade minimum required current supply 500 ma virtex family, industrial grade minimum required current supply 2 a notes: 1. ramp rate used for this specification is from 0 - 2.7 vdc. peak current occurs on or near the internal power-on reset thresho ld of 1.0v and lasts for less than 3 ms. 2. devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above. 3. larger currents can result if ramp rates are forced to be faster. input/output standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma lvttl (1) ? 0.5 0.8 2.0 5.5 0.4 2.4 24 ? 24 lvcm os 2 ? 0.5 .7 1.7 5.5 0.4 1.9 12 ? 12 pci, 3.3 v ? 0.5 44% v ccint 60% v ccint v cco + 0.5 10% v cco 90% v cco note 2 note 2 pci, 5.0 v ? 0.5 0.8 2.0 5.5 0.55 2.4 note 2 note 2 gtl ? 0.5 v ref ? 0.05 v ref + 0.05 3.6 0.4 n/a 40 n/a gtl+ ? 0.5 v ref ? 0.1 v ref + 0.1 3.6 0.6 n/a 36 n/a hstl i (3) ? 0.5 v ref ? 0.1 v ref + 0.1 3.6 0.4 v cco ? 0.4 8 ? 8 hstl iii ? 0.5 v ref ? 0.1 v ref + 0.1 3.6 0.4 v cco ? 0.4 24 ? 8 hstl iv ? 0.5 v ref ? 0.1 v ref + 0.1 3.6 0.4 v cco ? 0.4 48 ? 8 sstl3 i ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.6 v ref + 0.6 8 ? 8 sstl3 ii ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.8 v ref + 0.8 16 ? 16 sstl2 i ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.61 v ref + 0.61 7.6 ? 7.6 sstl2 ii ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.80 v ref + 0.80 15.2 ? 15.2 ctt ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.4 v ref + 0.4 8 ? 8 agp ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 10% v cco 90% v cco note 2 note 2 notes: 1. v ol and v oh for lower drive currents are sample tested. 2. tested according to the relevant specifications. 3. dc input and output levels for hstl18 (hstl i/o standard with v cco of 1.8 v) are provided in an hstl white paper on www.xilinx.com .
virtex? 2.5 v field programmable gate arrays r ds003-3 (v3.2) september 10, 2002 www.xilinx.com module 3 of 4 production product specification 1-800-255-7778 5 virtex switching characteristics all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test pat- terns. listed below are representative values. for more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. all timing parameters assume worst-case operating conditions (supply voltage and junc- tion temperature). values apply to all virtex devices unless otherwise noted. iob input switching characteristics input delays associated with the pad are specified for lvttl levels. for other standards, adjust the delays with the values shown in , page 6 . description device symbol speed grade units min -6 -5 -4 propagation delays pad to i output, no delay all t iopi 0.39 0.8 0.9 1.0 ns, max pad to i output, with delay xcv50 t iopid 0.8 1.5 1.7 1.9 ns, max xcv100 0.8 1.5 1.7 1.9 ns, max xcv150 0.8 1.5 1.7 1.9 ns, max xcv200 0.8 1.5 1.7 1.9 ns, max xcv300 0.8 1.5 1.7 1.9 ns, max xcv400 0.9 1.8 2.0 2.3 ns, max xcv600 0.9 1.8 2.0 2.3 ns, max xcv800 1.1 2.1 2.4 2.7 ns, max xcv1000 1.1 2.1 2.4 2.7 ns, max pad to output iq via transparent latch, no delay all t iopli 0.8 1.6 1.8 2.0 ns, max pad to output iq via transparent latch, with delay xcv50 t ioplid 1.9 3.7 4.2 4.8 ns, max xcv100 1.9 3.7 4.2 4.8 ns, max xcv150 2.0 3.9 4.3 4.9 ns, max xcv200 2.0 4.0 4.4 5.1 ns, max xcv300 2.0 4.0 4.4 5.1 ns, max xcv400 2.1 4.1 4.6 5.3 ns, max xcv600 2.1 4.2 4.7 5.4 ns, max xcv800 2.2 4.4 4.9 5.6 ns, max xcv1000 2.3 4.5 5.1 5.8 ns, max sequential delays clock clk all minimum pulse width, high t ch 0.8 1.5 1.7 2.0 ns, min minimum pulse width, low t cl 0.8 1.5 1.7 2.0 ns, min clock clk to output iq t iockiq 0.2 0.7 0.7 0.8 ns, max
virtex? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v3.2) september 10, 2002 6 1-800-255-7778 production product specification setup and hold times with respect to clock clk at iob input register (1) setup time / hold time pad, no delay all t iopick /t ioickp 0.8 / 0 1.6 / 0 1.8 / 0 2.0 / 0 ns, min pad, with delay xcv50 t iopickd /t ioickpd 1.9 / 0 3.7 / 0 4.1 / 0 4.7 / 0 ns, min xcv100 1.9 / 0 3.7 / 0 4.1 / 0 4.7 / 0 ns, min xcv150 1.9 / 0 3.8 / 0 4.3 / 0 4.9 / 0 ns, min xcv200 2.0 / 0 3.9 / 0 4.4 / 0 5.0 / 0 ns, min xcv300 2.0 / 0 3.9 / 0 4.4 / 0 5.0 / 0 ns, min xcv400 2.1 / 0 4.1 / 0 4.6 / 0 5.3 / 0 ns, min xcv600 2.1 / 0 4.2 / 0 4.7 / 0 5.4 / 0 ns, min xcv800 2.2 / 0 4.4 / 0 4.9 / 0 5.6 / 0 ns, min xcv1000 2.3 / 0 4.5 / 0 5.0 / 0 5.8 / 0 ns, min ice input all t ioiceck /t iockice 0.37/ 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, max set/reset delays sr input (iff, synchronous) all t iosrcki 0.49 1.0 1.1 1.3 ns, max sr input to iq (asynchronous) all t iosriq 0.70 1.4 1.6 1.8 ns, max gsr to output iq all t gsrq 4.9 9.7 10.9 12.5 ns, max notes: 1. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed "best-case" , but if a "0" is listed, there is no positive hold time. 2. input timing for lvttl is measured at 1.4 v. for other i/o standards, see table 3 . description device symbol speed grade units min -6 -5 -4
virtex? 2.5 v field programmable gate arrays r ds003-3 (v3.2) september 10, 2002 www.xilinx.com module 3 of 4 production product specification 1-800-255-7778 7 iob input switching characteristics standard adjustments iob output switching characteristics output delays terminating at a pad are specified for lvttl with 12 ma drive and fast slew rate. for other standards, adjust the delays with the values shown in iob output switching characteristics standard adjustments , page 9 . description symbol standard (1) speed grade units min-6-5-4 data input delay adjustments standard-specific data input delay adjustments t ilvttl lv t t l 0 0 0 0 n s t ilvcmos2 lv c m o s 2 ? 0.02 ? 0.04 ? 0.04 ? 0.05 ns t ipci33_3 pci, 33 mhz, 3.3 v ? 0.05 ? 0.11 ? 0.12 ? 0.14 ns t ipci33_5 pci, 33 mhz, 5.0 v 0.13 0.25 0.28 0.33 ns t ipci66_3 pci, 66 mhz, 3.3 v ? 0.05 ? 0.11 ? 0.12 ? 0.14 ns t igtl gtl 0.100.200.230.26 ns t igtlp gtl+ 0.06 0.11 0.12 0.14 ns t ihstl hstl 0.02 0.03 0.03 0.04 ns t isstl2 sstl2 ? 0.04 ? 0.08 ? 0.09 ? 0.10 ns t isstl3 sstl3 ? 0.02 ? 0.04 ? 0.05 ? 0.06 ns t ictt ctt 0.010.020.020.02 ns t iagp agp ? 0.03 ? 0.06 ? 0.07 ? 0.08 ns notes: 1. input timing for lvttl is measured at 1.4 v. for other i/o standards, see ta bl e 3 . description symbol speed grade units min-6-5-4 propagation delays o input to pad t ioop 1.2 2.9 3.2 3.5 ns, max o input to pad via transparent latch t ioolp 1.4 3.4 3.7 4.0 ns, max 3-state delays t input to pad high-impedance (1) t iothz 1.0 2.0 2.2 2.4 ns, max t input to valid data on pad t ioton 1.4 3.1 3.3 3.7 ns, max t input to pad high-impedance via transparent latch (1) t iotlphz 1.2 2.4 2.6 3.0 ns, max t input to valid data on pad via transparent latch t iotlpon 1.6 3.5 3.8 4.2 ns, max gts to pad high impedance (1) t gts 2.5 4.9 5.5 6.3 ns, max sequential delays clock clk minimum pulse width, high t ch 0.8 1.5 1.7 2.0 ns, min minimum pulse width, low t cl 0.8 1.5 1.7 2.0 ns, min
virtex? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v3.2) september 10, 2002 8 1-800-255-7778 production product specification clock clk to pad delay with obuft enabled (non-3-state) t iockp 1.0 2.9 3.2 3.5 ns, max clock clk to pad high-impedance (synchronous) (1) t iockhz 1.1 2.3 2.5 2.9 ns, max clock clk to valid data on pad delay, plus enable delay for obuft t iockon 1.5 3.4 3.7 4.1 ns, max setup and hold times before/after clock clk (2) setup time / hold time o input t ioock /t iocko 0.51 / 0 1.1 / 0 1.2 / 0 1.3 / 0 ns, min oce input t iooceck /t iockoce 0.37 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min sr input (off) t iosrcko /t iockosr 0.52 / 0 1.1 / 0 1.2 / 0 1.4 / 0 ns, min 3-state setup times, t input t iotck /t iockt 0.34 / 0 0.7 / 0 0.8 / 0 0.9 / 0 ns, min 3-state setup times, tce input t iotceck /t iocktce 0.41 / 0 0.9 / 0 0.9 / 0 1.1 / 0 ns, min 3-state setup times, sr input (tff) t iosrckt /t iocktsr 0.49 / 0 1.0 / 0 1.1 / 0 1.3 / 0 ns, min set/reset delays sr input to pad (asynchronous) t iosrp 1.6 3.8 4.1 4.6 ns, max sr input to pad high-impedance (asynchronous) (1) t iosrhz 1.6 3.1 3.4 3.9 ns, max sr input to valid data on pad (asynchronous) t iosron 2.0 4.2 4.6 5.1 ns, max gsr to pad t iogsrq 4.9 9.7 10.9 12.5 ns, max notes: 1. 3-state turn-off delays should not be adjusted. 2. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed "best-case ", but if a "0" is listed, there is no positive hold time. description symbol speed grade units min-6-5-4
virtex? 2.5 v field programmable gate arrays r ds003-3 (v3.2) september 10, 2002 www.xilinx.com module 3 of 4 production product specification 1-800-255-7778 9 iob output switching characteristics standard adjustments output delays terminating at a pad are specified for lvttl with 12 ma drive and fast slew rate. for other standards, adjust the delays by the values shown. description symbol standard (1) speed grade unit s min-6-5-4 output delay adjustments standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, csl) t olvttl_s2 lvttl, slow, 2 ma 4.2 14.7 15.8 17.0 ns t olvttl_s4 4 ma 2.5 7.5 8.0 8.6 ns t olvttl_s6 6 ma 1.8 4.8 5.1 5.6 ns t olvttl_s8 8 ma 1.2 3.0 3.3 3.5 ns t olvttl_s12 12 ma 1.0 1.9 2.1 2.2 ns t olvttl_s16 16 ma 0.9 1.7 1.9 2.0 ns t olvttl_s24 24 ma 0.8 1.3 1.4 1.6 ns t olvttl_f2 lvttl, fast, 2ma 1.9 13.1 14.0 15.1 ns t olvttl_f4 4 ma 0.7 5.3 5.7 6.1 ns t olvttl_f6 6 ma 0.2 3.1 3.3 3.6 ns t olvttl_f8 8 ma 0.1 1.0 1.1 1.2 ns t olvttl_f12 12 ma 0 0 0 0 ns t olvttl_f16 16 ma ? 0.10 ? 0.05 ? 0.05 ? 0.05 ns t olvttl_f24 24 ma ? 0.10 ? 0.20 ? 0.21 ? 0.23 ns t olvcmos2 lvcmos2 0.10 0.10 0.11 0.12 ns t opci33_3 pci, 33 mhz, 3.3 v 0.50 2.3 2.5 2.7 ns t opci33_5 pci, 33 mhz, 5.0 v 0.40 2.8 3.0 3.3 ns t opci66_3 pci, 66 mhz, 3.3 v 0.10 ? 0.40 ? 0.42 ? 0.46 ns t ogtl gtl 0.6 0.50 0.54 0.6 ns t ogtlp gtl+ 0.7 0.8 0.9 1.0 ns t ohstl_i hstl i 0.10 ? 0.50 ? 0.53 ? 0.5 ns t ohstl_iii hstl iii ? 0.10 ? 0.9 ? 0.9 ? 1.0 ns t ohstl_iv hstl iv ? 0.20 ? 1.0 ? 1.0 ? 1.1 ns t osstl2_i sstl2 i ? 0.10 ? 0.50 ? 0.53 ? 0.5 ns t osslt2_ii sstl2 ii ? 0.20 ? 0.9 ? 0.9 ? 1.0 ns t osstl3_i sstl3 i ? 0.20 ? 0.50 ? 0.53 ? 0.5 ns t osstl3_ii sstl3 ii ? 0.30 ? 1.0 ? 1.0 ? 1.1 ns t octt ctt 0 ? 0.6 ? 0.6 ? 0.6 ns t oagp agp 0 ? 0.9 ? 0.9 ? 1.0 ns notes: 1. output timing is measured at 1.4 v with 35 pf external capacitive load for lvttl. for other i/o standards and different loads, see ta bl e 2 and ta b l e 3 .
virtex? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v3.2) september 10, 2002 10 1-800-255-7778 production product specification calculation of t ioop as a function of capacitance t ioop is the propagation delay from the o input of the iob to the pad. the values for t ioop were based on the standard capacitive load (csl) for each i/o standard as listed in ta b l e 2 . for other capacitive loads, use the formulas below to calcu- late the corresponding t ioop . t ioop = t ioop + t opadjust + (c load ? c sl ) * fl where: t opadjust is reported above in the output delay adjustment section. c load is the capacitive load for the design. table 2: constants for calculating t ioop standard csl (pf) fl (ns/pf) lvttl fast slew rate, 2ma drive 35 0.41 lvttl fast slew rate, 4ma drive 35 0.20 lvttl fast slew rate, 6ma drive 35 0.13 lvttl fast slew rate, 8ma drive 35 0.079 lvttl fast slew rate, 12ma drive 35 0.044 lvttl fast slew rate, 16ma drive 35 0.043 lvttl fast slew rate, 24ma drive 35 0.033 lvttl slow slew rate, 2ma drive 35 0.41 lvttl slow slew rate, 4ma drive 35 0.20 lvttl slow slew rate, 6ma drive 35 0.100 lvttl slow slew rate, 8ma drive 35 0.086 lvttl slow slew rate, 12ma drive 35 0.058 lvttl slow slew rate, 16ma drive 35 0.050 lvttl slow slew rate, 24ma drive 35 0.048 lv c mo s2 3 5 0 . 04 1 pci 33mhz 5v 50 0.050 pci 33mhz 3.3 v 10 0.050 pci 66 mhz 3.3 v 10 0.033 gtl 0 0.014 gtl+ 0 0.017 hstl class i 20 0.022 hstl class iii 20 0.016 hstl class iv 20 0.014 sstl2 class i 30 0.028 sstl2 class ii 30 0.016 sstl3 class i 30 0.029 sstl3 class ii 30 0.016 ctt 20 0.035 agp 10 0.037 notes: 1. i/o parameter measurements are made with the capacitance values shown above. see application note xapp133 on www.xilinx.com for appropriate terminations. 2. i/o standard measurements are reflected in the ibis model information except where the ibis format precludes it. ta b l e 3 : delay measurement methodology standard v l (1) v h (1) meas. point v ref typ (2) lv t t l 0 3 1 . 4 - lv c m o s 2 0 2 . 5 1 . 1 2 5 - pci33_5 per pci spec - pci33_3 per pci spec - pci66_3 per pci spec - gtl v ref ? 0.2 v ref +0.2 v ref 0.80 gtl+ v ref ? 0.2 v ref +0.2 v ref 1.0 hstl class i v ref ? 0.5 v ref +0.5 v ref 0.75 hstl class iii v ref ? 0.5 v ref +0.5 v ref 0.90 hstl class iv v ref ? 0.5 v ref +0.5 v ref 0.90 sstl3 i & ii v ref ? 1.0 v ref +1.0 v ref 1.5 sstl2 i & ii v ref ? 0.75 v ref +0.75 v ref 1.25 ctt v ref ? 0.2 v ref +0.2 v ref 1.5 agp v ref ? (0.2xv cco ) v ref + (0.2xv cco ) v ref per agp spec notes: 1. input waveform switches between v l and v h . 2. measurements are made at vref (typ), maximum, and minimum. worst-case values are reported. 3. i/o parameter measurements are made with the capacitance values shown in table 2 . see application note xapp133 on www.xilinx.com for appropriate terminations. 4. i/o standard measurements are reflected in the ibis model information except where the ibis format precludes it.
virtex? 2.5 v field programmable gate arrays r ds003-3 (v3.2) september 10, 2002 www.xilinx.com module 3 of 4 production product specification 1-800-255-7778 11 clock distribution guidelines clock distribution switching characteristics description device symbol speed grade units -6 -5 -4 global clock skew (1) global clock skew between iob flip-flops xcv50 t gskewiob 0.10 0.12 0.14 ns, max xcv100 0.12 0.13 0.15 ns, max xcv150 0.12 0.13 0.15 ns, max xcv200 0.13 0.14 0.16 ns, max xcv300 0.14 0.16 0.18 ns, max xcv400 0.13 0.13 0.14 ns, max xcv600 0.14 0.15 0.17 ns, max xcv800 0.16 0.17 0.20 ns, max xcv1000 0.20 0.23 0.25 ns, max notes: 1. these clock-skew delays are provided for guidance only. they reflect the delays encountered in a typical design under worst-c ase conditions. precise values for a particular design are provided by the timing analyzer. description symbol speed grade units min -6 -5 -4 gclk iob and buffer global clock pad to output. t gpio 0.33 0.7 0.8 0.9 ns, max global clock buffer i input to o output t gio 0.34 0.7 0.8 0.9 ns, max
virtex? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v3.2) september 10, 2002 12 1-800-255-7778 production product specification i/o standard global clock input adjustments description symbol standard (1) speed grade units min -6 -5 -4 data input delay adjustments standard-specific global clock input delay adjustments t gplvttl lv t t l 0 0 0 0 n s , max t gplvcmos 2 lv c m o s 2 ? 0.02 ? 0.04 ? 0.04 ? 0.05 ns, max t gppci33_3 pci, 33 mhz, 3.3 v ? 0.05 ? 0.11 ? 0.12 ? 0.14 ns, max t gppci33_5 pci, 33 mhz, 5.0 v 0.13 0.25 0.28 0.33 ns, max t gppci66_3 pci, 66 mhz, 3.3 v ? 0.05 ? 0.11 ? 0.12 ? 0.14 ns, max t gpgtl gtl 0.7 0.8 0.9 0.9 ns, max t gpgtlp gtl+ 0.7 0.8 0.8 0.8 ns, max t gphstl hstl 0.7 0.7 0.7 0.7 ns, max t gpsstl2 sstl2 0.6 0.52 0.51 0.50 ns, max t gpsstl3 sstl3 0.6 0.6 0.55 0.54 ns, max t gpctt ctt 0.7 0.7 0.7 0.7 ns, max t gpagp agp 0.6 0.54 0.53 0.52 ns, max notes: 1. input timing for gplvttl is measured at 1.4 v. for other i/o standards, see ta b l e 3 .
virtex? 2.5 v field programmable gate arrays r ds003-3 (v3.2) september 10, 2002 www.xilinx.com module 3 of 4 production product specification 1-800-255-7778 13 clb switching characteristics delays originating at f/g inputs vary slightly according to the input used. the values listed below are worst-case. precise values are provided by the timing analyzer. description symbol speed grade units min-6-5-4 combinatorial delays 4-input function: f/g inputs to x/y outputs t ilo 0.29 0.6 0.7 0.8 ns, max 5-input function: f/g inputs to f5 output t if5 0.32 0.7 0.8 0.9 ns, max 5-input function: f/g inputs to x output t if5x 0.36 0.8 0.8 1.0 ns, max 6-input function: f/g inputs to y output via f6 mux t if6y 0.44 0.9 1.0 1.2 ns, max 6-input function: f5in input to y output t f5iny 0.17 0.32 0.36 0.42 ns, max incremental delay routing through transparent latch to xq/yq outputs t ifnctl 0.31 0.7 0.7 0.8 ns, max by input to yb output t byyb 0.27 0.53 0.6 0.7 ns, max sequential delays ff clock clk to xq/yq outputs t cko 0.54 1.1 1.2 1.4 ns, max latch clock clk to xq/yq outputs t cklo 0.6 1.2 1.4 1.6 ns, max setup and hold times before/after clock clk (1) setup time / hold time 4-input function: f/g inputs t ick /t cki 0.6 / 0 1.2 / 0 1.4 / 0 1.5 / 0 ns, min 5-input function: f/g inputs t if5ck /t ckif5 0.7 / 0 1.3 / 0 1.5 / 0 1.7 / 0 ns, min 6-input function: f5in input t f5inck /t ckf5in 0.46 / 0 1.0 / 0 1.1 / 0 1.2 / 0 ns, min 6-input function: f/g inputs via f6 mux t if6ck /t ckif6 0.8 / 0 1.5 / 0 1.7 / 0 1.9 / 0 ns, min bx/by inputs t dick /t ckdi 0.30 / 0 0.6 / 0 0.7 / 0 0.8 / 0 ns, min ce input t ceck /t ckce 0.37 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min sr/by inputs (synchronous) t rck t ckr 0.33 / 0 0.7 / 0 0.8 / 0 0.9 / 0 ns, min clock clk minimum pulse width, high t ch 0.8 1.5 1.7 2.0 ns, min minimum pulse width, low t cl 0.8 1.5 1.7 2.0 ns, min set/reset minimum pulse width, sr/by inputs t rpw 1.3 2.5 2.8 3.3 ns, min delay from sr/by inputs to xq/yq outputs (asynchronous) t rq 0.54 1.1 1.3 1.4 ns, max delay from gsr to xq/yq outputs t iogsrq 4.9 9.7 10.9 12.5 ns, max toggle frequency (mhz) (for export control) f tog (mhz) 625 333 294 250 mhz notes: 1. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed "best-case" , but if a "0" is listed, there is no positive hold time.
virtex? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v3.2) september 10, 2002 14 1-800-255-7778 production product specification clb arithmetic switching characteristics setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. precise values are provided by the timing analyzer. description symbol speed grade units min -6 -5 -4 combinatorial delays f operand inputs to x via xor t opx 0.37 0.8 0.9 1.0 ns, max f operand input to xb output t opxb 0.54 1.1 1.3 1.4 ns, max f operand input to y via xor t opy 0.8 1.5 1.7 2.0 ns, max f operand input to yb output t opyb 0.8 1.5 1.7 2.0 ns, max f operand input to cout output t opcyf 0.6 1.2 1.3 1.5 ns, max g operand inputs to y via xor t opgy 0.46 1.0 1.1 1.2 ns, max g operand input to yb output t opgyb 0.8 1.6 1.8 2.1 ns, max g operand input to cout output t opcyg 0.7 1.3 1.4 1.6 ns, max bx initialization input to cout t bxcy 0.41 0.9 1.0 1.1 ns, max cin input to x output via xor t cinx 0.21 0.41 0.46 0.53 ns, max cin input to xb t cinxb 0.02 0.04 0.05 0.06 ns, max cin input to y via xor t ciny 0.23 0.46 0.52 0.6 ns, max cin input to yb t cinyb 0.23 0.45 0.51 0.6 ns, max cin input to cout output t byp 0.05 0.09 0.10 0.11 ns, max multiplier operation f1/2 operand inputs to xb output via and t fandxb 0.18 0.36 0.40 0.46 ns, max f1/2 operand inputs to yb output via and t fandyb 0.40 0.8 0.9 1.1 ns, max f1/2 operand inputs to cout output via and t fandcy 0.22 0.43 0.48 0.6 ns, max g1/2 operand inputs to yb output via and t gandyb 0.25 0.50 0.6 0.7 ns, max g1/2 operand inputs to cout output via and t gandcy 0.07 0.13 0.15 0.17 ns, max setup and hold times before/after clock clk (1) setup time / hold time cin input to ffx t cckx /t ckcx 0.50 / 0 1.0 / 0 1.2 / 0 1.3 / 0 ns, min cin input to ffy t ccky /t ckcy 0.53 / 0 1.1 / 0 1.2 / 0 1.4 / 0 ns, min notes: 1. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed "best-case ", but if a "0" is listed, there is no positive hold time.
virtex? 2.5 v field programmable gate arrays r ds003-3 (v3.2) september 10, 2002 www.xilinx.com module 3 of 4 production product specification 1-800-255-7778 15 clb selectram switching characteristics description symbol speed grade units min -6 -5 -4 sequential delays clock clk to x/y outputs (we active) 16 x 1 mode t shcko16 1.2 2.3 2.6 3.0 ns, max clock clk to x/y outputs (we active) 32 x 1 mode t shcko32 1.2 2.7 3.1 3.5 ns, max shift-register mode clock clk to x/y outputs t reg 1.2 3.7 4.1 4.7 ns, max setup and hold times before/after clock clk (1) setup time / hold time f/g address inputs t as /t ah 0.25 / 0 0.5 / 0 0.6 / 0 0.7 / 0 ns, min bx/by data inputs (din) t ds /t dh 0.34 / 0 0.7 / 0 0.8 / 0 0.9 / 0 ns, min ce input (we) t ws /t wh 0.38 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min shift-register mode bx/by data inputs (din) t shdick 0.34 0.7 0.8 0.9 ns, min ce input (ws) t shceck 0.38 0.8 0.9 1.0 ns, min clock clk minimum pulse width, high t wph 1.2 2.4 2.7 3.1 ns, min minimum pulse width, low t wpl 1.2 2.4 2.7 3.1 ns, min minimum clock period to meet address write cycle time t wc 2.4 4.8 5.4 6.2 ns, min shift-register mode minimum pulse width, high t srph 1.2 2.4 2.7 3.1 ns, min minimum pulse width, low t srpl 1.2 2.4 2.7 3.1 ns, min notes: 1. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed "best-case ", but if a "0" is listed, there is no positive hold time.
virtex? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v3.2) september 10, 2002 16 1-800-255-7778 production product specification block ram switching characteristics tbuf switching characteristics jtag test access port switching characteristics description symbol speed grade units min-6-5-4 sequential delays clock clk to dout output t bcko 1.7 3.4 3.8 4.3 ns, max setup and hold times before/after clock clk (1) setup time / hold time addr inputs t back /t bcka 0.6 / 0 1.2 / 0 1.3 / 0 1.5 / 0 ns, min din inputs t bdck /t bckd 0.6 / 0 1.2 / 0 1.3 / 0 1.5 / 0 ns, min en input t beck /t bcke 1.3 / 0 2.6 / 0 3.0 / 0 3.4 / 0 ns, min rst input t brck /t bckr 1.3 / 0 2.5 / 0 2.7 / 0 3.2 / 0 ns, min wen input t bwck /t bckw 1.2 / 0 2.3 / 0 2.6 / 0 3.0 / 0 ns, min clock clk minimum pulse width, high t bpwh 0.8 1.5 1.7 2.0 ns, min minimum pulse width, low t bpwl 0.8 1.5 1.7 2.0 ns, min clka -> clkb setup time for different ports t bccs 3.0 3.5 4.0 ns, min notes: 1. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed "best-case ", but if a "0" is listed, there is no positive hold time. description symbol speed grade units min -6 -5 -4 combinatorial delays in input to out output t io 0000ns, max tri input to out output high-impedance t off 0.05 0.09 0.10 0.11 ns, max tri input to valid data on out output t on 0.05 0.09 0.10 0.11 ns, max description symbol speed grade units -6 -5 -4 tms and tdi setup times before tck t ta p t c k 4.0 4.0 4.0 ns, min tms and tdi hold times after tck t tcktap 2.0 2.0 2.0 ns, min output delay from clock tck to output tdo t tcktdo 11.0 11.0 11.0 ns, max maximum tck clock frequency f tck 33 33 33 mhz, max
virtex? 2.5 v field programmable gate arrays r ds003-3 (v3.2) september 10, 2002 www.xilinx.com module 3 of 4 production product specification 1-800-255-7778 17 virtex pin-to-pin output parameter guidelines all devices are 100% functionally tested. listed below are representative values for typical pin locations and normal clock loading. values are expressed in nanoseconds unless otherwise noted. global clock input to output delay for lvttl, 12 ma, fast slew rate, with dll global clock input-to-output delay for lvttl, 12 ma, fast slew rate, without dll description symbol device speed grade units min -6 -5 -4 lvttl global clock input to output delay using output flip-flop, 12 ma, fast slew rate, with dll. for data output with different standards, adjust delays with the values shown in output delay adjustments. t ickofdll xcv50 1.0 3.1 3.3 3.6 ns, max xcv100 1.0 3.1 3.3 3.6 ns, max xcv150 1.0 3.1 3.3 3.6 ns, max xcv200 1.0 3.1 3.3 3.6 ns, max xcv300 1.0 3.1 3.3 3.6 ns, max xcv400 1.0 3.1 3.3 3.6 ns, max xcv600 1.0 3.1 3.3 3.6 ns, max xcv800 1.0 3.1 3.3 3.6 ns, max xcv1000 1.0 3.1 3.3 3.6 ns, max notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. output timing is measured at 1.4 v with 35 pf external capacitive load for lvttl. the 35 pf load does not apply to the min va lues. for other i/o standards and different loads, see ta bl e 2 and ta bl e 3 . 3. dll output jitter is already included in the timing calculation. description symbol device speed grade units min -6 -5 -4 lvttl global clock input to output delay using output flip-flop, 12 ma, fast slew rate, without dll. for data output with different standards, adjust delays with the values shown in input and output delay adjustments. for i/o standards requiring v ref , such as gtl, gtl+, sstl, hstl, ctt, and ago, an additional 600 ps must be added. t ickof xcv50 1.5 4.6 5.1 5.7 ns, max xcv100 1.5 4.6 5.1 5.7 ns, max xcv150 1.5 4.7 5.2 5.8 ns, max xcv200 1.5 4.7 5.2 5.8 ns, max xcv300 1.5 4.7 5.2 5.9 ns, max xcv400 1.5 4.8 5.3 6.0 ns, max xcv600 1.6 4.9 5.4 6.0 ns, max xcv800 1.6 4.9 5.5 6.2 ns, max xcv1000 1.7 5.0 5.6 6.3 ns, max notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. output timing is measured at 1.4 v with 35 pf external capacitive load for lvttl. the 35 pf load does not apply to the min values. for other i/o standards and different loads, see ta bl e 2 and ta bl e 3 .
virtex? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v3.2) september 10, 2002 18 1-800-255-7778 production product specification minimum clock-to-out for virtex devices i/o standard with dll without dll all devices v50 v100 v150 v200 v300 v400 v600 v800 v1000 units *lvttl_s2 5.2 6.0 6.0 6.0 6.0 6.1 6.1 6.1 6.1 6.1 ns *lvttl_s4 3.5 4.3 4.3 4.3 4.3 4.4 4.4 4.4 4.4 4.4 ns *lvttl_s6 2.8 3.6 3.6 3.6 3.6 3.7 3.7 3.7 3.7 3.7 ns *lvttl_s8 2.2 3.1 3.1 3.1 3.1 3.1 3.1 3.2 3.2 3.2 ns *lvttl_s12 2.0 2.9 2.9 2.9 2.9 2.9 2.9 3.0 3.0 3.0 ns *lvttl_s16 1.9 2.8 2.8 2.8 2.8 2.8 2.8 2.9 2.9 2.9 ns *lvttl_s24 1.8 2.6 2.6 2.7 2.7 2.7 2.7 2.7 2.7 2.8 ns *lvttl_f2 2.9 3.8 3.8 3.8 3.8 3.8 3.8 3.9 3.9 3.9 ns *lvttl_f4 1.7 2.6 2.6 2.6 2.6 2.6 2.6 2.7 2.7 2.7 ns *lvttl_f6 1.2 2.0 2.0 2.0 2.1 2.1 2.1 2.1 2.1 2.2 ns *lvttl_f8 1.1 1.9 1.9 1.9 1.9 2.0 2.0 2.0 2.0 2.0 ns *lvttl_f12 1.0 1.8 1.8 1.8 1.8 1.9 1.9 1.9 1.9 1.9 ns *lvttl_f16 0.9 1.7 1.8 1.8 1.8 1.8 1.8 1.8 1.9 1.9 ns *lvttl_f24 0.9 1.7 1.7 1.7 1.8 1.8 1.8 1.8 1.8 1.9 ns lvcmos2 1.1 1.9 1.9 1.9 2.0 2.0 2.0 2.0 2.0 2.1 ns pci33_3 1.5 2.4 2.4 2.4 2.4 2.4 2.4 2.5 2.5 2.5 ns pci33_5 1.4 2.2 2.2 2.3 2.3 2.3 2.3 2.3 2.3 2.4 ns pci66_3 1.1 1.9 1.9 2.0 2.0 2.0 2.0 2.0 2.1 2.1 ns gtl 1.6 2.5 2.5 2.5 2.5 2.5 2.5 2.6 2.6 2.6 ns gtl+ 1.7 2.5 2.5 2.6 2.6 2.6 2.6 2.6 2.6 2.7 ns hstl i 1.1 1.9 1.9 1.9 1.9 2.0 2.0 2.0 2.0 2.0 ns hstl iii 0.9 1.7 1.7 1.8 1.8 1.8 1.8 1.8 1.8 1.9 ns hstl iv 0.8 1.6 1.6 1.6 1.7 1.7 1.7 1.7 1.7 1.8 ns sstl2 i 0.9 1.7 1.7 1.7 1.7 1.8 1.8 1.8 1.8 1.8 ns sstl2 ii 0.8 1.6 1.6 1.6 1.6 1.7 1.7 1.7 1.7 1.7 ns sstl3 i 0.8 1.6 1.7 1.7 1.7 1.7 1.7 1.7 1.8 1.8 ns sstl3 ii 0.7 1.5 1.5 1.6 1.6 1.6 1.6 1.6 1.6 1.7 ns ctt 1.0 1.8 1.8 1.8 1.9 1.9 1.9 1.9 1.9 2.0 ns agp 1.0 1.8 1.8 1.9 1.9 1.9 1.9 1.9 1.9 2.0 ns *s = slow slew rate, f = fast slew rate notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. input and output timing is measured at 1.4 v for lvttl. for other i/o standards, see ta bl e 3 . in all cases, an 8 pf external capacitive load is used.
virtex? 2.5 v field programmable gate arrays r ds003-3 (v3.2) september 10, 2002 www.xilinx.com module 3 of 4 production product specification 1-800-255-7778 19 virtex pin-to-pin input parameter guidelines all devices are 100% functionally tested. listed below are representative values for typical pin locations and normal clock loading. values are expressed in nanoseconds unless otherwise noted global clock set-up and hold for lvttl standard, with dll description symbol device speed grade units min -6 -5 -4 input setup and hold time relative to global clock input signal for lvttl standard. for data input with different standards, adjust the setup time delay by the values shown in input delay adjustments. no delay global clock and iff, with dll t psdll /t phdll xcv50 0.40 / ? 0.4 1.7 / ? 0.4 1.8 / ? 0.4 2.1 / ? 0.4 ns, min xcv100 0.40 / ? 0.4 1.7 / ? 0.4 1.9 / ? 0.4 2.1 / ? 0.4 ns, min xcv150 0.40 / ? 0.4 1.7 / ? 0.4 1.9 / ? 0.4 2.1 / ? 0.4 ns, min xcv200 0.40 / ? 0.4 1.7 / ? 0.4 1.9 / ? 0.4 2.1 / ? 0.4 ns, min xcv300 0.40 / ? 0.4 1.7 / ? 0.4 1.9 / ? 0.4 2.1 / ? 0.4 ns, min xcv400 0.40 / ? 0.4 1.7 / ? 0.4 1.9 / ? 0.4 2.1 / ? 0.4 ns, min xcv600 0.40 / ? 0.4 1.7 / ? 0.4 1.9 / ? 0.4 2.1 / ? 0.4 ns, min xcv800 0.40 / ? 0.4 1.7 / ? 0.4 1.9 / ? 0.4 2.1 / ? 0.4 ns, min xcv1000 0.40 / ? 0.4 1.7 / ? 0.4 1.9 / ? 0.4 2.1 / ? 0.4 ns, min iff = input flip-flop or latch notes: 1. set-up time is measured relative to the global clock input signal with the fastest route and the lightest load. hold time is measured relative to the global clock input signal with the slowest route and heaviest load. 2. dll output jitter is already included in the timing calculation. 3. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed "best-case ", but if a "0" is listed, there is no positive hold time.
virtex? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v3.2) september 10, 2002 20 1-800-255-7778 production product specification global clock set-up and hold for lvttl standard, without dll description symbol device speed grade units min -6 -5 -4 input setup and hold time relative to global clock input signal for lvttl standard. (2) for data input with different standards, adjust the setup time delay by the values shown in input delay adjustments. full delay global clock and iff, without dll t psfd /t phfd xcv50 0.6 / 0 2.3 / 0 2.6 / 0 2.9 / 0 ns, min xcv100 0.6 / 0 2.3 / 0 2.6 / 0 3.0 / 0 ns, min xcv150 0.6 / 0 2.4 / 0 2.7 / 0 3.1 / 0 ns, min xcv200 0.7 / 0 2.5 / 0 2.8 / 0 3.2 / 0 ns, min xcv300 0.7 / 0 2.5 / 0 2.8 / 0 3.2 / 0 ns, min xcv400 0.7 / 0 2.6 / 0 2.9 / 0 3.3 / 0 ns, min xcv600 0.7 / 0 2.6 / 0 2.9 / 0 3.3 / 0 ns, min xcv800 0.7 / 0 2.7 / 0 3.1 / 0 3.5 / 0 ns, min xcv1000 0.7 / 0 2.8 / 0 3.1 / 0 3.6 / 0 ns, min iff = input flip-flop or latch notes: notes: 1. set-up time is measured relative to the global clock input signal with the fastest route and the lightest load. hold time is measured relative to the global clock input signal with the slowest route and heaviest load. 2. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed "best-case ", but if a "0" is listed, there is no positive hold time.
virtex? 2.5 v field programmable gate arrays r ds003-3 (v3.2) september 10, 2002 www.xilinx.com module 3 of 4 production product specification 1-800-255-7778 21 dll timing parameters all devices are 100 percent functionally tested. because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. the following guidelines reflect worst-case values across the recommended operating conditions. dll clock tolerance, jitter, and phase information all dll output jitter and phase specifications determined through statistical measurement at the package pins using a clock mirror configuration and matched drivers. description symbol speed grade units -6 -5 -4 min max min max min max input clock frequency (clkdllhf) fclkinhf 60 200 60 180 60 180 mhz input clock frequency (clkdll) fclkinlf 25 100 25 90 25 90 mhz input clock pulse width (clkdllhf) t dllpwhf 2.0 - 2.4 - 2.4 - ns input clock pulse width (clkdll) t dllpwlf 2.5 - 3.0 3.0 - ns notes: 1. all specifications correspond to commercial operating temperatures (0 c to + 85 c). description symbol f clkin clkdllhf clkdll units min max min max input clock period tolerance t iptol - 1.0 - 1.0 ns input clock jitter tolerance (cycle to cycle) t ijitcc - 150 - 300 ps time required for dll to acquire lock t lock > 60 mhz - 20 - 20 s 50 - 60 mhz - - - 25 s 40 - 50 mhz - - - 50 s 30 - 40 mhz - - - 90 s 25 - 30 mhz - - - 120 s output jitter (cycle-to-cycle) for any dll clock output (1) t ojitcc 60 60 ps phase offset between clkin and clko (2) t phio 100 100 ps phase offset between clock outputs on the dll (3) t phoo 140 140 ps maximum phase difference between clkin and clko (4) t phiom 160 160 ps maximum phase difference between clock outputs on the dll (5) t phoom 200 200 ps notes: 1. output jitter is cycle-to-cycle jitter measured on the dll output clock, excluding input clock jitter. 2. phase offset between clkin and clko is the worst-case fixed time difference between rising edges of clkin and clko, excluding output jitter and input clock jitter. 3. phase offset between clock outputs on the dll is the worst-case fixed time difference between rising edges of any two dll outputs, excluding output jitter and input clock jitter. 4. maximum phase difference between clkin an clko is the sum of output jitter and phase offset between clkin and clko, or the greatest difference between clkin and clko rising edges due to dll alone ( excluding input clock jitter). 5. maximum phase difference between clock outputs on the dll is the sum of output jitter and phase offset between any dll clock outputs, or the greatest difference between any two dll output rising edges sue to dll alone ( excluding input clock jitter). 6. all specifications correspond to commercial operating temperatures (0 c to +85 c).
virtex? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v3.2) september 10, 2002 22 1-800-255-7778 production product specification revision history figure 1: frequency tolerance and clock jitter date version revision 11/98 1.0 initial xilinx release. 01/99 1.2 updated package drawings and specs. 02/99 1.3 update of package drawings, updated specifications. 05/99 1.4 addition of package drawings and specifications. 05/99 1.5 replaced fg 676 & fg680 package drawings. 07/99 1.6 changed boundary scan information and changed figure 11, boundary scan bit sequence. updated iob input & output delays. added capacitance info for different i/o standards. added 5 v tolerant information. added dll parameters and waveforms and new pin-to-pin input and output parameter tables for global clock input to output and setup and hold. changed configuration information including figures 12, 14, 17 & 19. added device-dependent listings for quiescent currents iccintq and iccoq. updated iob input and output delays based on default standard of lvttl, 12 ma, fast slew rate. added iob input switching characteristics standard adjustments. 09/99 1.7 speed grade update to preliminary status, power-on specification and clock-to-out minimums additions, "0" hold time listing explanation, quiescent current listing update, and figure 6 addra input label correction. added t ijitcc parameter, changed t ojit to t ophase . 01/00 1.8 update to speed.txt file 1.96. corrections for crs 111036,111137, 112697, 115479, 117153, 117154, and 117612. modified notes for recommended operating conditions (voltage and temperature). changed bank information for v cco in cs144 package on p.43. t clkin t clkin + t iptol period tolerance: the allowed input clock period change in nanoseconds. output jitter: the difference between an ideal reference clock edge and the actual design. _ ds003_20c_110399 i deal period actual period + jitter +/- jitter + maximum phase difference phase offset and maximum phase difference + phase offset
virtex ? 2.5 v field programmable gate arrays r ds003-3 (v3.2) september 10, 2002 www.xilinx.com module 3 of 4 production product specification 1-800-255-7778 23 virtex data sheet the virtex data sheet contains the following modules: ds003-1, virtex 2.5v fpgas: introduction and ordering information (module 1) ds003-2, virtex 2.5v fpgas: functional description (module 2) ds003-3, virtex 2.5v fpgas: dc and switching characteristics (module 3) ds003-4, virtex 2.5v fpgas: pinout tables (module 4) 01/00 1.9 updated dll jitter parameter table and waveforms, added delay measurement methodology table for different i/o standards, changed buffered hex line info and input/output timing measurement notes. 03/00 2.0 new tbcko values; corrected fg680 package connection drawing; new note about status of cclk pin after configuration. 05/00 2.1 modified "pins not listed ..." statement. speed grade update to final status. 05/00 2.2 modified table 18. 09/00 2.3 added xcv400 values to table under minimum clock-to-out for virtex devices . corrected units column in table under iob input switching characteristics . added values to table under clb selectram switching characteristics . 10/00 2.4 corrected pinout information for devices in the bg256, bg432, and bg560 packages in ta bl e 1 8 . corrected bg256 pin function diagram . 04/02/01 2.5 revised minimums for global clock set-up and hold for lvttl standard, with dll . converted file to modularized format. see the virtex data sheet section. 04/19/01 2.6 clarified tiockp and tiockon iob output switching characteristics descriptors. 07/19/01 2.7 under absolute maximum ratings , changed (t sol ) to 220 c . 07/26/01 2.8 removed t sol parameter and added footnote to absolute maximum ratings table. 10/29/01 2.9 updated the speed grade designations used in data sheets, and added ta b l e 1 , which shows the current speed grade designation for each device. 02/01/02 3.0 added footnote to dc input and output levels table. 07/19/02 3.1 removed mention of mil-m-38510/605 specification. added link to xapp158 from the power-on power supply requirements section. 09/10/02 3.2 added clock clk to iob input switching characteristics and iob output switching characteristics . date version revision
virtex ? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v3.2) september 10, 2002 24 1-800-255-7778 production product specification

▲Up To Search▲

Price & Availability of XCV150-5PQG240I

	To Download XCV150-5PQG240I Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .